rc extraction , Programming Skills, full-custom circuit layout verification, advanced semiconductor technology, physical verification tools, EMIR analysis, mixed signal analog high speed layout, Cadence Virtuoso, Circuit Design, device physics

CMOS/FinFET Process Technology (28nm and below), Analog Mixed-Signal Layout, DRC/LVS/LPE Verification, Deep Submicron Effects Mitigation, ESD and Latch-Up Design, EM/IR and Power Routing Considerations

Perl, Layout Design, floorplanning, Cadence VXL, Calibre LVS, FinFET