static timing analysis, Perl, Python, Tcl, power analysis, formal verification, Design for reliability, Physical Design, Physical Verification, tapeout

Routing, CTS, IP Block SoC Design, Timing optimization, Physical Verification, High-speed low power IP and custom circuit design, Cadence Innovus, High-speed NPU GPU CPU Subsystem RTL Integration, Synthesis, Placement, Synopsys ICC2 FC, Floor-planning

Matlab, Python, FD-SOI technologies, industrial testing, Cadence-Virtuoso, Digital Design, CMOS, millimetre-Wave architecture, Bi-CMOS, DFT test development, RF architecture, Analog Design

test program development , C, Test Methodology, Perl, Linux, Python, Dfm, high-speed digital testing, silicon process, Dft, ATE test solutions, Teradyne tester platforms, Advantest 93K

Solidworks, Power Bi, Tableau, Python

redhawk , Perl, Scripting Languages, Tcl, Dc, primetime, Quantus, Tempus, Voltus, Innovus, Star-RCXT, EDA Tools, Genus, PrimeRail