Software Release Management, Shell scripting, Deployment Git, WLAN standards IEEE 802.11, Automation using Python

C, Verilog, Scripting, RTL testbench debug, interconnects, Arm-based SoC architecture, memory hierarchy, Uvm, UPF, systemverilog, coverage closure, coherency

Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, ASIC Design, Power aware simulations, Verification, Validation, AHB

Python, FineSim, Synopsys VCS, Skill, Xcelium, Verilog-AMS, SystemVerilog-RNM, Cadence Virtuoso, Spectre

Arm, Python, RTL simulation, Debug, functional coverage closure, RISC-V, regression automation, x86 architecture, Uvm, SVA, systemverilog

Bus protocols - APB, C, Usb, Uart, Spi, Test Plan Creation, Pcie, I2c, System Verilog, Bus interconnects, Checkers, i2s, Uvm, Functional coverage, DP, Sd, AHB, Verification methodology, Gate-level simulations, Scoreboards, Gate Level Power-Aware simulations, Axi

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog