bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Questa tools, Axi, AMBA, Timing Constraints, ATPG, APB, microcontroller platforms, Cadence Virtuoso, AHB

Cloud infrastructure (AWS, Golang, Python, Infrastructure asset management, Automation development

rc extraction , Perl, Tcl, analog mixed-signal layouts, Skill, LVS, Dfm, Physical Verification, EMIR analysis, EDA Tools, ERC, DRC, Cadence Virtuoso, high-speed SerDes IPs

Ddr3, Spi, Uart, Usb, Logic Design, I2c, Pcie, AHB, Synthesis, formal verification, Custom SoC ASIC products, Static-timing closure, ddr2, Block-level function verification, Gate-level simulations, Micro-architecture, Rtl Design, UCL, Debug skills, CXL, D2D, Front-end design tools, Axi, Methodologies

Test Engineering, Python, Encryption and tunneling protocol test methods, Switching and routing protocols, L2-L3 network testing, Open source test and network traffic generating tools