Tcl Scripting, Python, System Verilog, HW–SW interaction, SoC TB architecture, test-plan creation, UPF-based methodologies, debug skills, UVM methodology, RTL integration, DV sign-off flows, gate-level simulation, power-aware verification

System Validation, SOC design, Design Verification

Ovm, System Verilog, RTL Debugging, Uvm, GPU architecture understanding, Test Bench bring-up, Emulation environments, Simulation environments, Test Plan development