C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design

System Verilog, Jtag, Python, Pcie, Perl, UVM methodology, High speed USB, UltraSoC, Design for Debug, RISC Debug Architecture, Tessent Embedded Analytics

C, Verilog, Verdi, Xcelium, JasperGold, Uvm, systemverilog