Tcl, C, Debugging, Shell, Verilog, System Verilog, Python, Perl, directed and constrained random methodologies, UVM methodology, Metric Driven Verification, assertions, formal verification methodologies

PCS, Mac, SVA, Ethernet architecture, Uvm, systemverilog, PHY interfaces

C, Python, LabVIEW, SoC System-on-Chip, precision measurement techniques, voltage regulators, reference circuits, bench characterization of Analog Digital and Mixed-Signal IPs, Microcontrollers

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, AMBA, Axi, UCIe, systemverilog

Ethernet, Pcie, Synopsys, Uvm, advanced verification methodologies, systemverilog, Mentor, Cadence, PAM4, Register modeling, D2D, protocol VIP integration, Avery, PAM2

System Verilog, UVM methodology