C, Makefile, Windows, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP-level ASIC verification, graphics pipeline knowledge, HLS tools, RTL code, Simulation Tools, UVM testbenches, automating workflows, simulation profile efficiency improvement, TLM, UVM based verification frameworks, debugging firmware

Jasper, Pcie, Verilog, System Verilog, Synopsys VC-Formal Magellan, formal property checking tools, Uvm, Cadence IEV, Synopsys VCS, HBM, Cadence IES, SVA

Verilog, System Verilog, Jasper, Simulation Tools, Synopsys VCS, Synopsys VC-Formal Magellan, Uvm, Cadence IES, Cadence IEV, Formal property checking tools

Jasper, Verilog, System Verilog, Synopsys VCS, Synopsys VC-Formal Magellan, Uvm, Cadence IES, Simulation Tools, Cadence IEV, Formal property checking tools