Dll, Dac, layout methodology, CADENCE layout entry tools, clock generation distribution, Broadband Analog, High-Speed Connectivity, LVS, Computing Storage-Memory Data-Transport, Pll, high-speed digital multi-GHz ADC, ERC, CALIBRE DRC, parasitic optimizing

clock distribution , Pll, transmitter front-end, serializer, Analog Design, Circuit Design, receiver front-end, wireline transceiver building blocks, deserializer, high speed analog design, FinFET technology