C, Usb, Makefile, Windows, Shell, Linux, Perl, Pcie, Verilog, Ethernet, Ruby, System Verilog, Systemc, IP level ASIC verification, acceleration HLS tools, Graphics pipeline knowledge, UVM testbenches, automating workflows in a distributed compute environment, AXI ACE Protocols, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, UVM based verification frameworks, TLM

Usb, Jtag, Perl, Pcie, Ethernet, System Verilog, Python, UVM methodology, Design for Debug, scripting in Linux Unix environments, SoC architecture verification, TSN, ARM based SoC verification, High speed USB

scoreboard , test environments , Test Cases, C, Shell, Soc Architecture, Verilog, Agents, Mixed signal designs, Verification testbenches, Debugging RTL and Gate simulations, Verification methodology, Monitors, Regression systems, Testbenches, Sequencers, Industry-standard simulators, Revision control systems, Directed and constrained random verification methodology

Perl, Shell scripting, Python, UVM Universal Verification Methodology, debugging RTL and gate level simulation issues, systemverilog

Windows, C, Systemc, Usb, Linux, Verilog, Makefile, Shell, Ruby, System Verilog, Ethernet, Perl, Pcie, Graphics pipeline knowledge, debugging firmware and RTL code using simulation tools, IP level ASIC verification, AXI ACE Protocols, UVM testbenches, HLS tools, TLM, simulation profile efficiency improvement, UVM based verification frameworks

Windows, C, Systemc, Usb, Linux, Verilog, Makefile, Shell, Ruby, System Verilog, Ethernet, Perl, Pcie, Graphics pipeline knowledge, debugging firmware and RTL code using simulation tools, IP level ASIC verification, automating workflows in a distributed compute environment, AXI ACE Protocols, UVM testbenches, HLS tools, TLM, simulation profile efficiency improvement, UVM based verification frameworks

HDL (Verilog/VHDL), Programming (C/C++/Python/Perl), Functional & Code Coverage Analysis, SoC Verification, RTL Debugging, Testbench Development

Fpga, Python, Perl, Uvm, object-oriented design, emulation platforms, RTL, AMBA bus protocols, test plan development, systemverilog, transaction level modeling

DDR, Perl, Pcie, Ethernet, Python, Tcl, checkers, debug methodologies, protocol monitors, verification planning, scalable reusable UVM testbenches, Uvm, assertion-based verification, testbench architectures, systemverilog, regression strategies, scoreboards, debugging skills, functional coverage, coverage models, performance verification

C, Systemc, Windows, Usb, Linux, Verilog, Makefile, Shell, Ruby, System Verilog, Ethernet, Pcie, Perl, acceleration HLS tools, debugging firmware and RTL code using simulation tools, Graphics pipeline knowledge, IP level ASIC verification, automating workflows in a distributed compute environment, AXI ACE Protocols, UVM testbenches, TLM, UVM based verification frameworks, simulation profile efficiency improvement