Verilog, Python, Perl, Gdb, SOC design, Indago, Cadence

Vcs, Gdb, Shell, Perl, Verilog, Python, ASIC design flow, floor-planning, Timing Analysis, Rtl Design, Eco, Debussy, bring-up lab debug

Cache, Soc Architecture, Verilog, power analysis, Synthesis, memory compression, FPGA design verification, digital logic design principles, systemverilog, logic synthesis techniques, RTL design concepts, FPGA and emulation platforms, Dft, fabric coherence, DRAM, low-power design techniques, assertion-based formal verification

random testing , Oops, Pcie, Verilog, Debugging, System Verilog, FPGA verification, coverage assertions, Ethernet based protocols, Otn, VCS simulation flow, Uvm, VMM, AXI memory controllers, adversarial testing

DDR, Perl, Verilog, Python, Tcl, spyglass, Axi, MIPI, AMBA, EDA Tools, Synopsys Design Compiler, LPDDR, AHB

UNIX, Tcl, System Verilog, Python, Perl, Synopsys Design Compiler, UPF, EDA Tools, Fusion Compiler, Innovus, ICC2, VHDL, primetime, Linux Shell, Formality, low-power design techniques