Verilog, multi-clock designs, Synthesis, formal verification, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Timing Concepts, asynchronous interfaces, System-Verilog

cache coherency , Verilog, Microarchitecture, Rtl Design, Digital Design, ip development

Soc Architecture, Physical design interaction, SoC integration, Formal verification techniques and tools, Verilog RTL development, UPF and low-power methodologies

Perl, Verilog, Python, Tcl, formal verification with Cadence LEC, Netlist CLP, Spyglass Lint CDC checks, UPF, clock domain crossing designs, Rtl Design, Synthesis, Logical Equivalence checks, low power design methodology

Uart, Spi, Can, Pcie, Verilog, I2c, Ddr3, Microchip Libero, MIL-STD-1553, Intel Quartus, SpaceFibre, systemverilog, Synopsys SpyGlass CDC, Xilinx Vivado, VHDL, SpaceWire, AXI4, Questa CDC

logic bist , static timing analysis, UNIX, Jtag, Perl, Linux, Tcl, DFT techniques, Synthesis, Scan Insertion, memory BIST, waveform debugging tools, Verilog simulator, equivalency checking, ATPG, EDA Tools, scan compression architecture, IEEE standards, SSN Scan, c-shell

catapult , Vcs, Ecos, Verilog, System Verilog, spyglass, LINT, Timing Analysis, Synopsys DC, cdc, Rtl Design, Verdi, VHDL, Stratus, Xcellium, SDC, Dft, Magillem, low power design methodologies

boot ROM, memory maps, reset synchronizer design, systemverilog, interrupt controllers, scan-enable muxing, power FSMs, BIST controllers, clock-gating cells, firmware bring-up, embedded microcontroller integration, reset-domain architecture