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Job Description:

Own the verification of complex blocks and subsystems within ARM-based SoCs.
Develop and maintain UVM/SystemVerilog-based verification environments.
Define test plans, implement constrained-random and directed tests, and drive coverage closure.
Debug RTL and testbench issues, perform root cause analysis, and collaborate with design teams to resolve bugs.
Analyze code and functional coverage metrics to ensure comprehensive verification.
Contribute to AI/automation initiatives for regression management, coverage tracking, and debug automation.
Work with architects and validation engineers to ensure end-to-end feature completeness and quality.
Provide technical guidance and mentorship to junior engineers as required.
Continuously improve verification methodology, reuse, and efficiency.

Requirements/Qualifications:

Bachelor's or Master's degree in Electrical/Electronics Engineering or related field.
7-9 years of experience in ASIC/SoC functional verification.
Strong expertise in SystemVerilog and UVM methodology.
Hands-on experience in developing block/subsystem/SoC-level verification environments.
Solid understanding of AMBA and PCIe protocols.
Good understanding of Digital Design, RTL fundamentals, and simulation/debug flows.
Familiarity with scripting (Python/TCL/Perl) for automation.
Exposure to AI/ML-based verification, emulation, or acceleration is a plus.
Strong analytical and debugging skills.
Excellent communication, teamwork, and problem-solving abilities.
Highly motivated, detail-oriented, and committed to delivering quality results.

Senior Engineer II-Verification