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Physical Design Expert

The Role

As a member of the Strategic Silicon Solution Group SOC Physical Design team, you will help bring to life cutting-edge designs.?You will work closely with the Full Chip/Subsystem Floorplan / Netlist, Tile/Block/Partition level Physical Design, Full Chip Static Timing Analysis and Constraints teams, to achieve first pass silicon success.

The Person

This person will be working on Full chip / Sub-system level Physical Design, Timing Analysis, Synthesis, Logical equivalence, Physical Verification, Power design/implementation/signoff, and will act as a mentor/coach/guide to Design Engineers. Will work very closely with Fellows, Principal Engineers, Architects, Technology/CAD teams and collaborate with cross functional worldwide teams. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills. Should have hands on Physical Design experience and must have handled RTL to GDS II at Top level or Hierarchical top level for at least few tape outs. Must have led physical design team/s in the capacity of technical lead or as a go to person.

Key Responsiblities

Physical design and timing closure at Tile/Partition/Subsystem/SOC level on a particular node
Automation to improve design PPA (Power, Performance, Area) and ensure a high-quality design environment for an SOC
Full chip level Die size estimation, Floor-planning, Power planning, IO planning, package compatibility, IO ring creation and ESD analysis
Full chip Hierarchical planning, block planning , block level constraints, hierarchical clock tree implementation, block integration and chip finishing.
Low power design with power estimation/optimization including clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption.
Full chip/Sub-system/Partition level Synthesis, Logic equivalence, implementation of low power UPF/CPF
Full chip / sub-system level constraints, MMMC & cross talk aware timing closure with latest OCV based analysis
RTL2GDSII design implementation and flow debug top down or bottoms up at chip level
PPA (Power, Performance, Area and Schedule) closure and flow development for key IPs like CPU, Graphics, Multimedia, Fabric cores and/or other critical sub-systems
Low Power signoff like Static and Dynamic power analysis at top level and/or sub-system level
Full chip / sub system level Clock tree synthesis and advanced clock tree implementation.
Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion and logic equivalence
Hands-on in reference flows, excellent debugging skills.
Maintain and update technology collaterals
Experience in 5nm & below technologies.

Preferred Experience

Minimum 10-15 years of relevant work experience.
Expertise in ICC2/ FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools.
Expertise in Signoff tools like Primetime for Timing, Calibre for DRC/LVS, Ansys Redhawk on EMIR, PT-PX for Power signoff
Should have worked as a go to person or technical lead for at least few full chip projects.
Strong technical leadership and ability to mentor/guide/coach design engineers to achieve and deliver project goals.
Strong inter-personal skills and ability to collaborate with teams spread across multiple geos.
Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts.
Must be using AI technologies in day to day problem solving

Academic Credentials

Bachelors or Master's degree in Computer/Electronics/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

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