Unix, Linux, Perl, Tcl, Low power verification, floorplanning, Placement, power analysis, PNR implementation

C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation

Physical Design Planning, Placement, Floor Planning

Verilog, System Verilog, python, Perl, Sta, Synthesis, Physical Verification, CTS, DFT tools, Extraction, Timing Analysis, Place And Route, Cadence, Synopsys

Clp, Sta, Timing Constraints, RTL synthesis, LEC, low-power design concepts

power optimization , FPGA Design, floorplanning, Place And Route, Timing Analysis, DRC/LVS Checks, Signal Integrity, Physical Verification, RTL Synthesis, Circuit Layout

Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology