static timing analysis, Python, Tcl, primetime, Tempus, high-speed design timing convergence, constraints synthesis, Clock Tree Synthesis, ECO flows

NDM Liberty .lib, Scripting, Timing Model Deliverables, AI-driven Automation, Physical Design, LibBuilder Flow, Library Management, AI-assisted Tools, MemView Generation, PVT Corner Coverage, LEF

Routing, DDR design knowledge, floorplanning, Calibre, primetime, Innovus, RTL-to-GDSII implementation, Placement, EDA Tools, Genus, Tcl tool scripting, Physical Design Methodologies, MultiTap-CTS

clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff

Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Signal Integrity, Leakage Power, Multi-Vt Flow, Dfm, IC design, Power Supply Management, Deep Sub-Micron Design Problems, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff

Physical Design, Physical Design Engineer, Automation script

power optimization , routing, Perl, Verilog, Python, Tcl, Synthesis, submicron process node technologies, Timing Analysis, power delivery methodologies, LVS, Power Estimation, formal verification, VHDL, layout verification methods, DRC, Placement, low-power design techniques, timing signoff, Clock Tree Synthesis

Scripting, Timing Model Deliverables, AI-driven Automation, Physical Design, LibBuilder Flow, Library Management, AI-assisted Tools, NDM Liberty, MemView Generation, LEF, PVT Corner Coverage

NDM Liberty .lib, Scripting, Timing Model Deliverables, AI-driven Automation, Physical Design, LibBuilder Flow, Library Management, MemView Generation, LEF, PVT Corner Coverage