Perl, Verilog, Python

Cache, Soc Architecture, Verilog, power analysis, Synthesis, memory compression, FPGA design verification, digital logic design principles, systemverilog, logic synthesis techniques, Dft, FPGA and emulation platforms, RTL design concepts, fabric coherence, DRAM, low-power design techniques, assertion-based formal verification

Spi, Uart, Verilog, Arm, System Verilog, I2c, Gpio, USB standards, Synopsys, ASIC design flow, Interconnect fabrics, Arteris fabrics, RTL Coding, Cadence, Scripting in Perl, Peripheral interface IPs, QSPI, I3C, System Verilog assertions, NoC architecture, Third-party IP integration, Axi

Uart, Spi, Gpio, Verilog, I2c, Arm, System Verilog, ASIC design flow, Interconnect fabrics, Cadence, Peripheral interface IPs, Arteris fabrics, System Verilog assertions, Axi, Scripting in Perl, APB, RTL Coding, Third-party IP integration, QSPI, I3C, Synopsys, USB standards, NoC architecture

Shell, Dsp, C, Perl, Verilog, Python, Systemc, AI-assisted verification tools, Uvm, systemverilog