Tcl Scripting, Jasper, Performance Verification, writing and debugging timing constraints, formal verification with Cadence LEC Synopsys Formality, Cadence RC Genus, Uvm, UPF, systemverilog, makefile flows, formal verification, Power-Aware Verification, multi-voltage power aware synthesis UPF flows, PtPx methodologies, Functional Verification, VC Formal, CPF, Synopsys Design Compiler DCG DC NXT Fusion Compiler

SAP, Htm, Microsoft Outlook, Renewable Technologies, INSRAE, H C Load, Feasibility Studies, Low Energy Designs, TM52, NBC, Bs, Hevacomp, Whole Life Carbon, Hap, IES, Mechanical Engineering, IES-Part L, Energy Strategies, Detailed Design Specification, CIBSE, ASHRAE

Verilog, Emulation, FPGA prototyping, Palladium, Veloce, Zebu, Protium

Scripting, C, C++, Verilog, System Verilog, Python, Large Logic design, Chip-Scope or equivalent, Questasim, Debug, Simulation, Modelsim, HDL design language