Perl, Python, constraint-random tests, Power-aware verification, formal static verification techniques, coverage-driven verification methodologies, Uvm, systemverilog

Verilog, FPGA Design, systemverilog, Uvm, SV Assertions, Testbench Development

x86 assembly language , C, Perl, Ovm, Arm, Python, SVTB, CPU Architecture, Uvm, Power Management Verification

simvision , python, perl, Verilog, Hspice, Xcellium, Finseim, MS RVM model writing, verilog a, SV PSL assertions, COSIM Mixed signal verification, Primesim, virtuoso, Waveview, SV UVM based Verification, SPICE testbenches

Gate level simulations, Functional Verification, DV strategies, Design Verification DV flow, protocols, mixed signal designs

Perl, Networking, AMBA