assertion based verification , Debugging Tools, Scripting Languages, systemverilog, Uvm, Testbench Development, FPGA Prototyping, coverage analysis, Design Simulation, Design Verification, Asic verification, SoC Verification

Ml, Perl, Python, Tcl, regression management, AMS Co-Simulation, Ai, mixed-signal verification, simulation coverage analysis, Uvm, systemverilog

catapult , Rtos, Sdk, Firmware, HLS cores, Vitis HLS, high-level synthesis, interconnect IPs, FPGA-based SoC applications, boot gen flows, SmartHLS, IP integration, bare-metal, Xilinx AMD Vitis flow, functional correctness, performance QoR timing, Testing Linux and Standalone Device Drivers, DMA, regression validation testing, Drivers, AXI memory hierarchies, general software engineering

Debug Root Cause Analysis, Verification Planning, Uvm, SoC Verification, systemverilog, Functional Coverage, Assertion-based Verification

Ovm, Database Management, Verilog, System Verilog, silicon debug, verification management tools, formal property checking tools, Uvm, memory controller protocols, assertion and metric-driven verification, Synopsys VCS, gate level simulation, power verification, reset verification, Cadence IES, contention checking, calibration board skew and jitter modeling