Mentor, Uvm, firmware interaction, Synopsys, AMs, systemverilog, Cadence, Siemens, Calibration and link training flows, Register models, industry VIPs, Avery, SERDES

Synopsys, Uvm, firmware interaction, AMs, Calibration, systemverilog, Mentor, Cadence, link training, Siemens, Register models, industry VIPs, Avery, SERDES

C, Shell, Verilog, Python, Test Planning, Tcl, Systemc, Transaction-level modeling using SystemVerilog, systemverilog, Assertions, Power-aware verification using UPF, Constrained-random verification, UVM-based testbench development, formal verification, NoC bus and interconnect verification

Arm, C, Python, Perl, Uvm, vManager, RISC-V Assembly, Cadence SKILL, systemverilog, Mixed Signal chips

Scala, Python, System Verilog, Chisel, Uvm