PERL, Tcl, Sta, Synthesis, CTS, Place Route, Full-chip Floor-planning, RTL2GDSII flow, ICC2, Physical Verification, Tempus, Make scripting, layout closure, timing convergence, primetime, Innovus, Physical Design, Timing Closure, high frequency design methodologies

Voltus, Backend Signoff flows, Cell EM, LVS, SigEM, Power Grid planning, pegasus, Cadence Tools, Innovus, PERC, EMIR, Tempus, Esd, Signal and Power bump planning, DRC

Routing, Perl, Shell scripting, Python, Tcl, EM Analysis, floorplanning, Cadence Innovus, Signal Integrity, UPF, Noise Analysis, Power Planning, Calibre, Physical Verification, Placement, Timing Closure, Low-Power Design methodologies, CPF, Physical Design implementation, Synopsys Fusion Compiler ICC2

routing, physical design flows, digital VLSI concepts, Tempus, floor-planning, Cadence Innovus, Voltus, Timing Closure, EDA Tools, Placement, Logic Synthesis, Rtl Design

Routing, floorplanning, Power Planning, CTS, Place And Route, Placement

Synthesis, PNR, Timing Closure, PV EM-IR Signoff

rc extraction , Ecos, Verification Tools, formal verification, Cross talk, Synthesis, Timing Closure, LVS, Physical Verification, Sta, Cadence synthesis, Scan Insertion, DRC, Physical design flow, PNR, Place And Route, Timing Analysis, RTL-GDSII, Dft, IR-EM checks