routing, RTL-to-GDS flows, Rtl Design, floorplanning, Physical Verification methodologies, Cadence, LVS, Physical Design, EDA Tools, ERC, Timing Closure, DRC, Placement, Synopsys, Siemens tools, Clock Tree Synthesis

Perl, Python, Tcl, UPF, DFT insertion, ATPG, IR-drop analysis, Constraints and SDC, Parasitics, Advanced nodes, Physical Verification, Timing Closure, schematic capture, Placement, Route to sign-off, Low-power implementation, Scan, Floorplan, Layout matching, Multiple power domains, Physical design process, Netlists

Python, Tcl, EDA Tools, PrimeClosure, floorplanning, CTS, Innovus, Aspen, Sta, ICC2, IO Timing ECO, Physical Design, Tempus, Postroute Optimization, Seahawk, Placement, Timing Closure, DRC closure, EMIR drop

Unix, Linux, Perl, Tcl, STA flows, floorplanning, Placement, power analysis, PNR implementation

Voltus, Backend Signoff flows, Cell EM, LVS, SigEM, Power Grid planning, pegasus, Cadence Tools, Innovus, PERC, EMIR, Tempus, Esd, Signal and Power bump planning, DRC

redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus

power optimization , routing, Perl, Python, Tcl, physical design flows, floorplanning, digital VLSI concepts, IR-drop, Timing Analysis, Tempus, voltus, Cadence Innovus, LVS, EM analysis, Physical Verification, Rtl Design, EDA Tools, DRC, Placement

Static Timing Analysis, routing, chip finishing, LVS, clock-tree synthesis, Dfm, Physical Verification, DRC, Floorplan design, congestion reduction techniques, Low Power implementation, hierarchical designs, parasitic extractions, sign-off requirements, Synthesis, placement guidelines, place route flow, timing optimizations