C, MATLAB, Python, Perl, Parasitic Extraction, systemverilog, Verilog-A, RF ADE, Spectre, Mixed-Signal Verification, CMOS, Cadence Virtuoso, SERDES

C, Python, Perl, MATLAB, Parasitic Extraction, High-speed SerDes circuits, systemverilog, Mixed-signal verification, Verilog-A, Cadence Virtuoso, RF ADE, Spectre

Verilog, Tcl, Ethernet, Perl, C, Scripting Languages, Pcie, AHB, Flash interfaces, RDC constructs, IP Synthesis, IP development flow, QuadSPI, FPGA Emulation Board, Axi, SERDES, BUS Protocols, HDLs, DDR4, High Speed Serial protocols, ATPG, cdc, AMBA, Testplan development, VHDL, microcontroller architecture, pre silicon validation, LPDDR4, Dft