Linux, Perl, Python, Tcl, Synopsys Custom Compiler, Layout automation, VoltusXFA, Calibre, Skill, Totem, Physical Verification, Pulsic Unity Itools, PDN analysis tools, Cadence Virtuoso, ICV

PDK updates, DRC debugging, FPGA SOC full chip physical verification, RDL Bump Ubump development, FinFet technology, SOC RDL development, PDK DRC LVS rule files, Full chip integration, Hierarchical layout handling, 3D integration of AoA or SSIT designs, Parasitic Extraction

PV fixing, Esd, DRC, Innovas