PDN, Physical Verification, IR Drop, EM analysis, LVS, Antenna Checks

Unix, Clp, Linux, Perl, Integration, Scripting, Tcl, floorplanning, LEC, PNR, STA flows, Placement, Optimization, ASIC Design, Verification, PDN, Validation

CMOS layout fundamentals, LVS closure, DRC closure, Analog custom layout techniques, Physical verification flows, FinFET technology nodes, Cadence Virtuoso, Parasitic Extraction, Reliability checks, Layout automation, Physical verification tools, Layout methodologies, ERC, Device matching and symmetry, Scripting in Tcl