rc extraction , routing, Tempus, LVS, Cadence layout tools, Innovus, STA timing closure, ERC, DRC, Placement, Caliber tool, IR EM analysis, block level low power aware floorplanning, tape out activities, Clock Tree Synthesis

static timing analysis, Synthesis, signal integrity analysis, pads log management, Place And Route, RDL routing, Floor Planning, EDA tools for physical design and verification, power grid design, full-chip physical design, Timing Closure, bump placement, Clock Tree Synthesis

clocking , noise analysis, UCIe standard concepts, Signal Integrity, analog circuit theory, advanced packaging technologies

clocking , noise analysis, UCIe standard concepts, Signal Integrity, advanced packaging technologies, analog circuit theory