device physics matching techniques, OPAMP circuits, Oscillators, Cadence Layout tools Virtuoso, Temperature Sensor, ESD Latchup mitigation techniques, VXL compliance, Mentor Graphics verification tools Calibre, analog and mixed-signal layout techniques, Custom Analog Layout, DACs, Bandgaps, Bias Circuits, ADCs, circuit parasitic extraction reduction, LDOs, Physical Verification LVS DRC ERC ANT with Calibre

IR drop, digital design fundamentals, LVS, Cadence Innovus, Physical Verification, crosstalk, MMMC setup and hold closure, block-level timing analysis, physical design implementation, AI-assisted tools, DRC, EM noise, Synopsys IC Compiler II