debugging complex IP designs, UVM methodology, test plan reviews, testbench development, systemverilog

automation, Ovm, Tcl Scripting, Verilog, Perl, Uvm, GLS, RTL, SV, SDF sim debug, Specman, test-bench development, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification

System Verilog, Pcie, Uvm, PXC, CXL, RTL Design using Verilog