Perl, Verilog, Python, Tcl, Synthesis, object-oriented programming, floorplanning, Place And Route, VHDL, RTL-to-GDSII implementation, EDA Tools, Timing Closure, Clock Tree Synthesis

synopsys primetime , Pvs, Perl, Python, Tcl, Mentor Calibre, Cadence Pegasus, PowerSI, ICC2, clock gating, Cadence Innovus, Synopsys Fusion Compiler, UPF, Synopsys IC Validator, Ansys RedHawk, CPF