Makefile, Windows, Shell, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, debugging firmware and RTL code, graphics pipeline knowledge, HLS tools, Simulation Tools, UVM testbenches, automating workflows, simulation profile efficiency improvement, TLM, UVM based verification frameworks

Systemc, Windows, Linux, Makefile, Shell, Verilog, Ruby, System Verilog, Perl, TLM, graphics pipeline knowledge, Simulation Tools, IP level ASIC verification, debugging firmware and RTL code, automating workflows, UVM testbenches, HLS tools, simulation profile efficiency improvement, UVM based verification frameworks

Test Planning, Perl, Firmware, Ruby, System Verilog, Graphics

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware and RTL code using simulation tools

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools