Vcs, Python, Verilator, Uvm, systemverilog

Vcs, Python, Verilator, Uvm, systemverilog

Verilog, CPU architecture, debugging skills, UVM based Testbench development, systemverilog

Vcs, Python, Verilator, Uvm, systemverilog

arm architecture , C, Python, System Verilog, verification methodologies and tools, CPU microarchitecture verification

Vcs, Xcelium, Questa, Uvm, systemverilog

Vcs, Python, Verilator, Uvm, systemverilog

hardware engineering , Digital Logic Design, Embedded Firmware, Scripting Languages, Jtag, Verilog, System Verilog, IEEE1500, Micro-processor debug, Power management verification, Memory dump, MBIST, UPF, Assertions, C Language, Scan dump, DFT architecture, formal verification

C, Ovm, virtualization, Perl, Python, Tcl, Client Server centric CPU features, SystemVerilog Assertions, cache controllers, x86 assembly, semi randomized test generators, FPGA HW platforms, Uvm, systemverilog, Validation using Emulation, validation strategy development, memory coherency, debugging test failures, power management, AI based methodologies in Validation, coverage driven Validation methodologies