Perl, Verilog, Python, Tcl, VHDL, Static Verification, systemverilog, Rtl Design

AI ML concepts, physical design tools such as Synopsys Fusion Compiler, scripting and automation using Python

boundary scan , Jtag, Perl, Scripting Languages, Python, Tcl, SOC design, DFT architectures, MBIST, Sram, Synopsys STAR memory system, Scan, Rom, ATPG, DFX, register files