sentinel , Incident Management, Team Management, SOC Operations

Test Planning, Ovm, Debugging, CHI, Uvm, system simulation tools, AHB, UVM-based test benches, SoC design verification, APB, Axi, emulation models, AMBA protocols

Siemens Tessent, RTL-level DFT insertion, Cadence Modus, netlist handling, ATPG simulations, SpyGlass for DFT linting, SOC-level pattern retargeting, PDL standards, Mixed-Signal DFT methodologies, Streaming Scan Network SSN, Synopsys TestMAX TetraMAX

Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Asynchronous interface, Synthesis, SDCC, RTL Coding, micro-architecture, Low power SoC design, System-Verilog, constraint development, SOC design, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB

Jtag, Perl, Python, Tcl, MBIST, Siemens Tessent, Synopsys TestMAX SMS, DFT protocols, iJTAG, IEEE 1687, SoC DFT architecture and design, Cadence Modus, EDA Tools, Scan Compression, IEEE 1149.1, LBIST

automation, use case development, threat detection, incident response processes, cybersecurity frameworks, SIEM platforms, log ingestion, technology-driven innovation, Process Optimization, Cyber Kill Chain, Trend Analysis, GSOC operations

SoC Verification, systemverilog, universal verification methodology

arm architecture , Usb, DDR, Perl, Pcie, Test Plan, Scripting, Python, Shell Programming, Tcl, Arm core, GIC, SMMU, Dms, verification checks, Arm system IP, verification plan, debug methodology, SoC Verification

Soc Architecture, systemverilog, CAD Tools, Rtl Design, SoC Integration, Asic

San, Linux, Networking, Weblogic