Perl, System Verilog, Tcl, Code functional coverage, Ethernet MAC PCS and SerDes SoC verification, Checkers, Cadence, Uvm, Constrained random verification, BFMs, Block system level verification plans and tests, Gate-level SDF simulations, Scoreboards, Monitors, Ethernet Subsystem SoC verification, Synopsys

Cism, CCISO, Cissp, Client Service, MDR delivery, SOC operations

Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification

Tcl, Python, Perl, SoC DFT architecture and design

arm architecture , C, Ovm, Jtag, Perl, Verilog, Python, System Verilog, CPU architecture, interconnects, Uvm, power management techniques, debug architecture protocols, coherent fabrics, VHDL, SoC Verification, SVTB

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Integration, Power Bi, JIRA, Confluence, Sta, Validation, Tapeout, SoC design flows, Verification, Physical Design, Dft, MS Project, ip development

C Programming, System Verilog, DSP Image RADAR processing, SOC Chip level Cluster Sub-System Verification, Interconnect NIC FlexNoC Cache Coherency, Uvm, Microcontroller and Microprocessor architecture, ARM Cores

Networking, PowerShell, Threat Hunting, Linux Internals, Python, KQL, Detection-as-code, Active Directory, Incident response lifecycle, MITRE ATT&CK framework, Wazuh, Microsoft Sentinel, Threat intelligence platforms, SOAR platforms