Software Automation, System Validation, Debug Lab Equipment, Protocol Interface Validation, ATE Expertise, Bench Characterization, Post-Silicon Functional Validation, SoC Validation Expertise, Wafer Probe CP

shell scripting, Verilog, Python, Tcl, Sta, SDC constraints, cdc, synchronizers, multi-reset SoC designs, asynchronous FIFOs, systemverilog, reset sequencing, RDC, debugging RTL timing, LINT, synthesis tools

C, Makefile, Soc Architecture, Windows, Perl, Linux, Verilog, Python, System Verilog, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification

Register Abstraction Layer (RAL), SoC integration, UVM-based verification methodologies, AMBA protocols, coverage-driven verification, systemverilog

C, Makefile, Soc Architecture, Windows, Linux, Perl, Verilog, System Verilog, Python, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification

Python, Usb, Tcl, Verilog, Arm, Bash, Pcie, Perl, Uvm, System-Verilog, SVA, RISC-V, waveform debugging tools, LPDDR4, SoC Design Verification, power management, PSS

Soc Architecture, MCU architecture, system-level design, IP selection, interconnect, NPU