cdc, Dft, Synthesis, DV debug, Debug, RTL Coding, Rtl Design, ip design

Digital Logic Design, Scripting, RTL Coding, Clock domain crossing analysis, Lint checks, Static-timing-analysis, ECO flows

C, testbenches, Emulation, Simulation, RTL, Digital Design, CPU verification, Uvm, coverage models

Spi, DDR, Shell, Pcie, Debugging, I2c, Python, Scripting, Uart, Perl, Ethernet, Tcl, SoC emulation, Boot flow, High-speed protocols, HBM, ZeBu, emulation platforms, Memory interfaces, Palladium, system initialization, Security Architecture, Peripheral interfaces, Veloce, CXL, USB 3.0

Logic Design, Perl, Python, Tcl, Sta, MBIST OCC validation flows, Mentor, Cadence, Physical design flows, SpyGlass DFT rules, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, Digital Circuit Design, SSN design and IEEE 1687 IJTAG standards, Synopsys, RTL design synthesis