Static Timing analysis, Perl, Tcl, Clock Planning, Implementation PnR Signoff, Parasitic Extraction, Floor Planning, Power Plan, Digital place and route, Constraint development, Place And Route, High speed SoC designs, Clock Tree Synthesis

redhawk , Shell, Python, Tcl, SC CADENCE, PDK collateral development, semiconductor device physics, Voltus, Calibre, EDA Tools, EMIR tool flows, Reliability verification, SVRF, ESD PERC design rules

Linux, Perl, Python, Tcl, CAD flows, Skill, EDA Tools

Tcl Scripting, Ovm, Unix Shell Scripting, Perl, Verilog, Ethernet, System Verilog, CMOS logic design, IC chip design development flow process, Uvm, Circuit Analysis, CAE CAD tools, JESD, Axi, VHDL, Circuit Design, AHB, coverage assertion driven verification

UNIX, Perl, System Verilog, Python, Tcl, primetime, Fusion Compiler, ICC2, Formality, UPF, Innovus, VHDL, EDA Tools, Synopsys Design Compiler, Linux Shell, low-power design techniques