Solidworks, Overmolding, Siemens Nx, Moldflow simulation analysis, Injection Molding, DFM reviews, Creo, Engineering plastics

matching , rc extraction , shielding , bandgap references , Perl, Tcl, ADC, latch-up strategies, Skill, high-speed analog custom layout, LVS, Power Planning, Dfm, Pll, clock routing, SERDES, Esd, EDA Tools, ERC, EMIR analysis, DRC, Cadence Virtuoso, LDOs

Dac, Perl, Tcl, GAA nodes, ADC, Skill, FinFET, deep sub-micron CMOS, LVS, Dfm, Pll, SERDES, ERC, EMIR analysis, EDA Tools, DRC, Cadence Virtuoso

Debugging Tools, Cadence LVS, RMAP, Verification Tools, Caliber DRC, ERC, LVS verification, Virtuoso XL

Design Patterns, Java, Git, Software Architecture, Agile Methodologies, Api Development, Debugging, Python, Performance optimization

ESD concepts, JEDEC DDR interface requirements, ASIC design flow, DDR Timing, analog mixed signal design methodologies, SDRAM functionality, CMOS Circuit Design, layout methodologies, ODT

C, Mobility, Debugging, Automation Frameworks, Log Analysis, LTE stack, EPC core, air interface S1AP, UE L1 SW development, eNodeB, IMS server, 3GPP protocols, Volte, RRH and handover testing, IETF Standards, RAN platform architecture, LTE 4G eNodeB verification, gNodeB, Troubleshooting, UE simulators, L1 schedulers, Wireless Packet Core Standards

analog circuits , Unix Environment, DDR, shell scripting, Verilog, Python, Models, memory subsystems, digital design processes, simulation debugging, RTL, Uvm, top-level integration, systemverilog, Schematics, VerilogAMS