Verilog, Computer Architecture, verification methodologies, Uvm, systemverilog

scoreboard , Perl, Scripting Languages, Python, Uvm, Agents, constrained random techniques, sequencers, HVLs, testbenches, Gate simulations, debugging RTL, monitors

System Verilog, Python, I2c, Uart, Uvm, Assertions, Gate-Level, Coverage, ASIC