Spi, DDR, Shell, Pcie, Debugging, I2c, Scripting, Python, Uart, Perl, Ethernet, Tcl, Boot flow, SoC emulation, High-speed protocols, ZeBu, HBM, emulation platforms, Memory interfaces, Palladium, system initialization, Security Architecture, Peripheral interfaces, Veloce, CXL, USB 3.0

C, Uart, Spi, Shell, Verilog, Ethernet, I2c, Python, Systemc, Tcl, SVI3, systemverilog, Axi, formal verification, DMA, UVM-based testbench development, AHB, power-aware verification UPF, NoC bus and interconnect verification

matching , Ml, Eda, DDR, ERC, LVS, interface IPs, high-speed layout, Design Automation, Ai, Reliability, ONFI, Python scripts, full-custom layouts, SVRF, Esd, DRC, signal parasitics, Power Planning, FinFET nodes, Latch-up, Skill, SERDES, Floorplan

Vcs, Uvm, coverage analysis, Verification Planning, PCIe/Ethernet/USB/DDR protocols, Waveform Analyzers

C, Matlab, Python, SW Verification Validation, Ethernet communication stack, CAN bus communication protocols, Stateflow, ARINC429, Simulink, Assembly Programming

test mode timing constraints definition, Genus Synopsys, DFT concepts, TetraMax DFTMax, Scan Insertion, Transition delay test coverage analysis, simulating test vectors, equivalence check DFT DRC rules, ATPG coverage analysis, Cadence Encounter Test, timing fixes corrective actions for timing violations, ASIC DFT