CMOS process and circuit design, Analog/Mixed-signal design fundamentals, ASIC design flow, JEDEC DDR interface standards, ESD concepts, Circuit layout methodology

bandgap references , Comparators, Statistics, MOS Diodes, Transistor layout fabrication process, Analog Circuit Design, Monte Carlo analysis, Level Shifter, Schmitt Trigger, Statistical Distributions, Schematic generation, LDMOS, ESD protection circuits for CMOS IC, Power FETs, Amplifiers, Current Mirrors

bandgap references , temperature sensors , AC simulations, Schematic Maestro, frequency response, mixed-signal circuit design, low-noise Sigma-Delta converters, DC operating point, op-amps, mismatch analysis, biasing circuits, noise, INL, precision analog circuits, DNL, Stability, CMOS technologies, ADEXL, Layout XL, LDOs, THD, Spectre AMS, Cadence Virtuoso suite

analog CMOS design, mixed-signal ADC design, sensor interfaces, LDOs, Cadence Tools, DACs, Sigma-Delta ADCs, circuit simulations

Verilog, Usb, Tcl, Arm, System Verilog, Ethernet, Perl, Spi, I2c, Python, Soc Architecture, LINT, ASIC design flow, Timing Analysis, peripheral IPs, Synthesis, Low-power design, Axi, power estimations, BUS Protocols, MBIST, Bus Matrix design, MIPS, AMBA, Rtl Design, timing constraint SDC, DFT concepts, RDC, Formal CDC

Spi, Soc Architecture, Verilog, I2c, System Verilog, Python, Usb, Perl, Ethernet, Arm, Tcl, Bus Matrix design, MIPS, DFT concepts, Rtl Design, Synthesis, RDC, Peripheral IPs, Power estimations, Timing constraint SDC, ASIC design flow, LINT, Formal CDC, MBIST, AMBA, Axi, BUS Protocols, Low-power design, Timing Analysis

Cadence Virtuoso, analog and mixed-signal circuit design, high-speed analog architectures, Signal Integrity, jitter, Spectre, advanced CMOS technology nodes

rtl development , Fpga, LINT, cdc, ASIC, RTL Netlist, RTL Coding, hardware design tools, front end design flow