synthesis and place & route, high-speed interface protocols (PCIe, MIPI), Asic Physical Design, Synopsys Fusion Compiler, HDMI, timing and power optimization, RTL to GDSII flow

Perl, Verilog, Python, Tcl, Pre-Silicon test planning, low power concepts, RTL design for DFT, MBIST, DFT methodologies, systemverilog, Siemens Mentor Tessent, DFT Compiler, ATPG, Synopsys TetraMAX, DFT Integration Verification, Scan, Memory Repair, IJTAG

pipelining , Ecos, Perl, Python, Tcl, Clock gating, Design DFT, UPF, Low-power design implementation, MCMM synthesis, Physical Synthesis, Netlist delivery, STA timing closure, Multi-clock domain designs, Power optimization flows, Timing Constraints, Synthesis methodologies, Timing constraints validation, formal verification