CMOS/FinFET Technology (28nm and below), Analog Mixed-Signal Layout, DDR/HBM IP Design, ASIC Physical Design Flow, Floorplanning and DRC/LVS Verification, Layout Automation Scripting

rc extraction , Programming Skills, full-custom circuit layout verification, advanced semiconductor technology, physical verification tools, EMIR analysis, mixed signal analog high speed layout, Cadence Virtuoso, Circuit Design, device physics

rc extraction , Automation, Programming Skills, Full-custom circuit layout verification, Circuit Design, Dfm, LVS, Cadence Virtuoso, DRC, Mixed signal analog high speed layout, EMIR analysis

UNIX, Matlab, Signal analysis, Analog digital circuit design, MOS transistors, CMOS and BCD parasitic junctions, Parasitic analysis, Circuit simulation tools, Layout tradeoffs, CMOS fabrication processes, Analog Mixed Signal IC design, AD DC analysis, system modeling