Frontend and backend ASIC design flows (DV, Experience with EDA tools (Cadence Virtuoso, Python, Perl, TCL scripting for CAD tool automation, RTL coding and Verilog proficiency, RTL, Synopsys Custom Compiler, FC/ICC2

hardware engineering , Test Planning, System Verilog, testbench stimulus agent monitor checker development, coverage driven constraint random verification, Uvm, c based reference model, unit and IP level verification