python, perl, Physical Design

layout verification , Tcl, static timing analysis, Python, Perl, Floor Planning, physical design tools, noise analysis, RTL to GDS workflows, equivalence verification, Clock Tree Synthesis

redhawk , Tcl, Perl, VSLP, Synthesis, ICC, Logic equivalence checking, Low Power checking, Calibre, Power signal integrity, Physical Design Verification, SDC clean up, Place And Route, DRC, Physical Design, SOC design, Mixed signal block integration, Dc, Timing Closure, LVS, Pt, STA timing, Deep sub-micron designs, Formality, Manufacturability