Python, Tcl, Synthesis, SDC, QoR

Java, Oracle Integration Cloud, Pl Sql, J2EE, Ldap, Sql, Nosql, Oracle Service Bus, Perl, Mulesoft, Python, RDMS, AD Object Storage

snowflake , Apache Airflow, Numpy, Pandas, Unix Shell Scripting, Python, Sql, ELT, Etl, dbt

C, Usb, Mercurial, Svn, Git, DDR, Perl, Pcie, Ethernet, Arm, Python, Tcl, UVM methodology, RISC-V, AMBA, SoC level verification, UVM based verification environments, OVM based methodologies, Design Verification infrastructure

Cache, Soc Architecture, Verilog, power analysis, Synthesis, memory compression, FPGA design verification, digital logic design principles, systemverilog, logic synthesis techniques, Dft, FPGA and emulation platforms, RTL design concepts, fabric coherence, DRAM, low-power design techniques, assertion-based formal verification

composer , Nginx, Tomcat, BigQuery, Shell Scripting, Apache, Apache Airflow, Git, Docker, Terraform, Kubernetes, Python, GitOps, Pipelines, Github Actions, Google Cloud Services, Oracle Weblogic Database, DAGs, YAML files

System Verilog, Python, Tcl, RTL synthesis tool development, UPF, parallel algorithms, formal verification, Dft, VHDL, RTL gate level logic optimizations, RTL synthesis technology, RTL design IP development, power synthesis, logic optimizations, Dynamic Power