KEY RESPONSIBILITIES:

Define and drive key Frontend/Beckend/Physical Design methodologies.
Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows.
Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug.
Work closely with design teams to gather requirements and develop strategies to tackle key technical problems.
Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR
Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk

PREFERRED EXPERIENCE:

8+ years of professional experience in physical design, preferably with high performance designs.
Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.
Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
Versatility with scripts to automate design flow.
Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
Excellent physical design and timing background.
Strong analytical/problem solving skills and pronounced attention to details.

MTS Silicon Design Engineer (AECG ASIC TFM Lead)