Digital Forensics, Incident Response, Splunk, Qradar, malware behaviour, Sentinel One, KQL, GCP security monitoring, Microsoft Defender XDR, automation workflows, threat actor tactics, CrowdStrike, SIEM technologies, Python Scripts, Microsoft Sentinel, attack techniques, SOAR platforms

arm architecture , C, Ovm, Jtag, Perl, Verilog, Python, System Verilog, CPU architecture, interconnects, Uvm, power management techniques, debug architecture protocols, coherent fabrics, VHDL, SoC Verification, SVTB

C, Verilog, Scripting, RTL testbench debug, interconnects, Arm-based SoC architecture, memory hierarchy, Uvm, UPF, systemverilog, coverage closure, coherency

Rtos, C, Nvme, Pcie, Firmware Development, Renode, SoC interfaces, qemu, Zephyr OS, AMBA, C-based SDKs, on-chip memory interfaces, Simulation, Bare metal, AHB, DRAM DDR controllers

arm architecture , Test Plans, C, C++, ACE lite or CHI bus protocols, CPU architecture, Coherent and non-coherent fabric IPs and protocols, PCIe Controller PHY IPs and protocols, DDR protocols, pre-silicon SoC verification, Memory Controller PHY IPs, performance verification, Coverage, checkers, Emulation, test generators, test benches

Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, ASIC Design, Power aware simulations, Verification, Validation, AHB

Embedded Software, Systemc, Python, MATLAB, Soc Architecture, system-level modeling, performance simulation, DSP algorithms, Analog Circuit Design, high-speed SerDes system architecture, digital RTL

DDR, Pcie, Ethernet, GIC, CMN, Low-Speed Peripherals, SMMU, RISC-V Cores, eMMC, CoreSight, SoC-level Design Verification, SV, Low-Power Verification, ARM v8 v7 Cores, Uvm, UPF