DRC LVS clean signoff, Functional and physical ECOs, Placement and optimization, Physical design implementation, floorplanning, Setup hold timing closure, Timing convergence, Power grid design, Routing and post-route optimization

Placement and optimization, Timing convergence, Power grid design, Physical design implementation, DRC LVS clean signoff, Automation through scripting, Functional and physical ECOs, Routing and post-route optimization, Methodology improvements, floorplanning, Setup hold timing closure

Cadence PVS, IC Validator ICV, ASIC Physical Design flow, CMOS layout concepts, Physical Verification tools, GDSII OASIS formats, advanced technology nodes