Scripting, Computer Architecture, Perl, Pcie, Verilog, Object Oriented Programming, System Verilog, Python, Automation of verification processes, Asic verification, UVM based verification frameworks, CXL

Scripting, Pcie, Perl, Verilog, Object Oriented Programming, Python, System Verilog, UVM based verification frameworks, CXL, Asic verification

Bus protocols - APB, C, Usb, Uart, Spi, Test Plan Creation, Pcie, I2c, System Verilog, Bus interconnects, Checkers, i2s, Uvm, Functional coverage, DP, Sd, AHB, Verification methodology, Gate-level simulations, Scoreboards, Gate Level Power-Aware simulations, Axi

Pcie, Systemc, Jenkins, Python, Perl, MATLAB, Design Verification, DV, Design Verification Lead, IP Verification, Subsystem Verification, systemverilog, Uvm, formal verification, Functional Verification, Constraint Random, Coverage Closure, Verification Plan, Specman E, Xcelium, Vmanager, Verilog-A, RNM, C Modelling, ISO 26262, Semiconductor, Pre-Silicon Verification