monte carlo , Python, Functional Coverage, power management, Analog Mixed-Signal, Uvm, Assertions, systemverilog, Pvt, Verification Automation, Mixed-Signal Debug, RNM, AMS Verification, Verilog-AMS, Spice, AMS Simulation, PMIC

automation, Scripting, SoCs, Real model creation, mixed signal verification fundamentals, PSL SV assertions development, model validation, VerilogA, SV Verilog, environment development, verification planning, Verilog-AMS, verification of Power management IPs, behavioral modelling of analog blocks

System Verilog, Visual Studio Code, Uvm, Spectre, Cadence Xcelium-AMS, Hspice, Mixed-Signal verification, GitHub Copilot

Mentor, Uvm, firmware interaction, Synopsys, AMs, systemverilog, Cadence, Siemens, Calibration and link training flows, Register models, industry VIPs, Avery, SERDES

Verilog, Uvm, testbench creation, code coverage analysis, DFI protocols, logic simulation, systemverilog, Verilog-A, score boarding, AMS simulations, RTL debugging