Verilog, VHDL, Hardware static timing analysis, Testbench-driven hardware simulation, RTL linting technologies, Asynchronous clock domain crossing verification, systemverilog

Noc, C, Perl, Verilog, Python, power analysis, Synthesis, processor design, low power design techniques, arithmetic units, SoC designs, memory hierarchies, design of IPs and Subsystems, systemverilog, integration flows, Asic Design Verification, Fabrics, accelerators, micro-architecture, bus architectures

Vcs, Jenkins, Git, Pcie, Ethernet, Python, System Verilog, Tcl, Xcelium, SERDES, Uvm, GitLab CI, formal verification, Questa

cloud database , Pyspark, Scripting Languages, Shell, Gcp, Batch, Databricks, Azure, Python, AWS, Visualisation layer, statistical software