System Verilog, Building test benches from scratch, ASIC verification using UVM

Usb, Fpga, Perl, Pcie, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, test bench infrastructure, transaction level modeling, AXI4

Jasper, Perl, Python, Asic verification, formal property checking tools, Synopsys Magellan, systemverilog, Cadence IEV, verification methodologies and tools, VC Formal, functional coverage, SVA

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm

Vcs, Pcie, Python, Perl, Ethernet, Tcl, Xcelium, Uvm, Testbench Architecture, LPDDR4, Functional Coverage, Verdi, UCIe, systemverilog, Axi, MIPI, Constrained Random Verification, APB, DVE, USB4, USB3, Questa, CXL, DDR5, DDR4, AHB, SVA

code coverage , Vcs, Nlp, Test Plan Creation, verification closure, UVM methodology, non-NLP simulations, VS Code, systemverilog, GLS, GitHub CoPilot, debugging of complex mixed signal designs, testbench architecture, verification of mixed signal IP Design, Git version control, constraint-random test generation, failure root cause analysis, waveform debugs, functional coverage

Soc Architecture, System Verilog, digital design concepts, UVM Universal Verification Methodology, debugging using waveforms and logs

Verilog, random stimulus, VMM, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, systemverilog

C, coverage closure, coverage planning, Data-Consistency verification, power management verification, testbench development, clocking reset power-up sequences, low power verification flows, systemverilog

Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design